1. Field of the Invention
Example embodiments of the present invention relate to phase change random access memory (PRAM) devices and methods of operating the same.
2. Description of the Related Art
A PRAM device is a non-volatile memory device (e.g., a flash memory, ferroelectric RAM (FeRAM) and magnetic RAM (MRAM)). A PRAM device may be a memory device that writes and reads bit data using resistance characteristics of a phase change layer.
PRAMs and the other types of non-volatile memory may have some structural differences in storage nodes. In a phase transition temperature range, a PRAM storage node may use a phase change layer that changes the phase of a crystalline state of lower resistance to an amorphous state with a higher resistance. A portion of the phase change layer may contact a contact layer (e.g., a lower electrode contact layer as described below). The contact layer may contact a lower electrode. In the phase transition temperature range, the phase of a partial region of the phase change layer, which contacts the contact layer (e.g., the lower electrode contact layer), may change. The resistance characteristics of the phase change layer may change in relationship to the phase change.
FIG. 1 is a diagram illustrating a sectional view of a conventional PRAM device.
Referring to FIG. 1, a conventional PRAM device may have a transistor 2 on a silicon substrate 7. The transistor 2 may include a source region 3 and/or a drain region 4. The transistor 2 may also have a gate 5 formed on a channel region 6 between the source region 3 and the drain regions 4.
A conventional PRAM device may also include a storage node 10 connected to one of the source region 3 and the drain region 4 (e.g., the source region 3 of the transistor 2). The storage node 10 may be connected by a conductive plug 9 to the source region 3 or the drain region 4 of the transistor 2.
The storage node 10 may include a sequentially-stacked lower electrode 10a, lower electrode contact layer 10b, phase change layer 10c having written bit data and/or an upper electrode 10d. The lower electrode 10a may functions as a pad layer that provides a larger region on which the lower electrode contact layer 10b may be formed. The lower electrode contact layer 10b may contact a region restricted to a bottom surface of the phase change layer 10c. 
FIG. 2 is a diagram illustrating a method for using a conventional PRAM device as shown in FIG. 1. For the sake of brevity, FIG. 2 only illustrates the storage node 10.
Referring to FIG. 2, the phase of the phase change layer 10c designates a crystalline state as a set state. At the set state, it is assumed that a bit value 0 is recorded. When a bit value 0 is recorded in the phase change layer 10c, the upper electrode 10d may apply a first phase change current I1 through the phase change layer 10c on the lower electrode 10a. The first phase change current I1 may have an intensity h1. The first phase change current I1 may correspond to a reset voltage. The first phase change current I1 may change a phase of contact region A1 of the phase change layer 10c to an amorphous state. The first phase change current I1 is referred to as the reset current. The contact region A1 may contact the lower electrode contact layer 10b. The first phase change current I1 may be a pulse current, which has an application time of a few nanoseconds, and may have a higher current than a set current (described below in detail). The first phase change current I1 may be concentrated in the lower electrode contact layer 10b which has a smaller width than the phase change layer 10c. 
During application of the first phase change current I1, a region of the phase change layer 10c contacting the lower electrode contact layer 10b (e.g., the “contact region A1” described above) may exhibit an increase in resistance. A temperature of the region of the phase change layer 10c may also be greater than a phase transition temperature. The phase of the contact region A1 of the phase change layer 10c may change from a crystalline state to an amorphous state. An amorphous state of the contact region A1 of the phase change layer 10c may be designated as a reset state in which it is assumed that a bit value 1 is recorded.
When the contact region A1 of the phase change layer 10c is amorphous, a second phase change current I2 may be applied to the storage node 10 in the same direction as the first phase change current I1. Because the second phase change current I2 changes the phase of the contact region A1 of the phase change layer 10c from an amorphous state to its original crystalline state, it is referred to as the set current. The second phase change current I2 may be a pulse current. The second phase change current I2 may have an intensity h11. The intensity h11 may be lower than the intensity h1 of the first phase change current I1. An application time of the second phase change current I2 may be equal to or greater than an application time of the first phase change current I1.
While the second phase change current I2 is applied to the storage node portion 10, a resistance of the contact region A1 of the phase change layer 10c may increase, and a temperature of the contact region A1 may rise. Because the intensity h11 of the second phase change current I2 is lower than h1 and the application time of the second phase change current I2 is longer than the application time of the first phase change current I1, the temperature of the contact region A1 may remain below the phase transition temperature of the phase change layer 10c. Because the contact region A1 is heated over a longer period of time to a temperature lower than the phase transition temperature of the phase change layer 10c, the contact region A1 may change from an amorphous to a crystalline state. The entire phase change layer 10c may also be crystalline.
As described above, the resistance of the phase change layer 10c in the conventional PRAM device of FIG. 1 is determined by the first phase change current I1 and second phase change currents I2. The first phase change current I1 (e.g., the reset current) may impede the improvement of characteristics of the PRAM device.
In light of developments in semiconductor manufacturing technology, manufacturing smaller storage nodes and transistors in order to decrease the size of the PRAM device may not be technically difficult. As the size of the transistors becomes smaller, the current that the transistors may resist (e.g., the current that the transistors may withstand) may become smaller. It may be difficult to achieve higher integration of the PRAM device without decreasing the reset current.
A method of decreasing the reset current by reducing the width of the lower electrode contact layer is acknowledged by the conventional art.
FIG. 3 is a graph illustrating the relationship between the reset current and the width of the lower electrode contact layer (e.g., a change in the size of the contact region A1 of the phase change layer) in the conventional art.
Referring to FIG. 3, the size of the contact region A1 is proportional to the reset current. Therefore, as the size of the contact region A1 decreases, the reset current may decrease.
Other methods of decreasing the reset current have been proposed such as oxidizing the lower electrode contact layer 10b and/or using a higher resistance TiAlN layer as the lower electrode contact layer 10b. 
In the above methods for decreasing the reset current, the manufacturing yield and reliability of the PRAM device may decrease because the lower electrode contact layer produces an increased amount of Joule heating due to an increase in a set resistance.